In high-speed serial data communications, it is common practice to exchange data between first and second telecommunications systems. The first and second telecommunications systems may incorporate a serializer/deserializer (SERDES) circuit. In each SERDES circuit, a receiver is usually provided with a clock and data recovery (CDR) circuit for extracting a clock signal from incoming data. The performance of the CDR circuit is tied to its capacity to correctly recover transmitted data when a data period varies with time and/or when the data is subjected to jitter.
The jitter tolerance of the receiver, therefore, is significant when assessing a quality of the receiver data transfer. Jitter tolerance testing of high-speed SERDES circuits, however, is challenging. In particular, clock and data recovery testing of jitter tolerance is time consuming and difficult to represent under test.
The transmitter and receiver of transceiver circuits as well as the communication channel are sources of jitter within a communication system. For example, a transmitter may contribute jitter in the form of phase locked loop (PLL) random jitter, deterministic jitter and power noise injection. A deterministic jitter may be associated with a PLL, a clock tree, a data path, a driver and other similar elements of the communication system. The communication channel may provide jitter in the form of inter symbol interference based jitter, reflection, crosstalk, and power noise injection.
Conventionally, testing a receiver's jitter tolerance involves the use of measuring instruments and automated test equipment. Testing a receiver's jitter tolerance by this conventional method is an important but costly way of designing automated test equipment (ATE). To provide sufficient coverage for the receiver jitter tolerance performance, different jitter components and frequencies are introduced. The introduction of the different jitter components and frequencies, however, involves increased cost and complexity when implementing an ATE test of a receiver by externally injecting noise to a device under test (DUT).